The present invention relates to an information processing unit and a wiring design method suitable for the design of wiring layout of a semiconductor integrated circuit, and more particularly to an information processing unit and a wiring design method for realizing an efficiency of a wiring layout editing.
A related art (Laid-Open Hei 11-39365) checks the minimum clearance between wiring figures that are arranged by a layout design system and produces error figures 2600 indicative of error portions as shown in FIG. 26. The system of the related art indicates a portion that does not satisfy the conditions of the minimum clearance. FIG. 3 in the related art (Laid-Open Hei 11-39365) shows the technique that conducts the design rule check to produce the error figure.